The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor with a trim of the gate structure during etching of a BARC (bottom anti-reflective coating) layer from the top of the gate structure with the amount of trim of the gate structure being controlled by adjusting the doping of the gate electrode material comprising the gate structure.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension 104 and a source extension 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension 104 and the source extension 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate structure 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate structure 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where the MOSFET 100 is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate structure 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (SiN), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate structure 118 and the gate dielectric 116.
As the dimensions of the MOSFET 100 are further scaled down, the length of the gate structure 116 between the drain extension 104 and the source extension 106 are desired to be in a range of nanometers. Such a small dimension may be difficult to achieve using conventional photolithography patterning processes. In that case, the length of the gate structure 116 may be further trimmed down after the gate structure 116 is formed using conventional photolithography patterning processes. In such a trimming process, a mechanism for adjusting the amount of trim of the length of the gate structure is desired for controlling the length of the gate structure.
Accordingly, in a general aspect of the present invention, the gate structure of the field effect transistor is trimmed during etching of a BARC (bottom anti-reflective coating) layer from the top of the gate structure with the amount of trim of the gate structure being controlled by adjusting the doping of the gate electrode material comprising the gate structure.
In one embodiment of the present invention, for fabricating a field effect transistor within an active device area of a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate. A layer of gate electrode material is deposited on the layer of gate dielectric material, and the gate electrode material is a semiconductor material. One of an N-type dopant or a P-type dopant is implanted into the layer of gate electrode material such that the one of an N-type dopant or a P-type dopant has a dopant concentration in the layer of gate electrode material. A layer of BARC (bottom anti-reflective coating) material is then deposited on the layer of gate electrode material. A layer of photo-resist material is deposited, and the layer of photo-resist material, the layer of BARC (bottom anti-reflective coating) material, and the layer of gate electrode material are patterned to form a gate structure of the field effect transistor. The gate structure is comprised of the remaining gate electrode material, and the BARC (bottom anti-reflective coating) material remains on the gate structure. The photo-resist material is removed from the BARC (bottom anti-reflective coating) material remaining on top of the gate structure.
The BARC (bottom anti-reflective coating) material is then stripped from the gate structure using an etching reactant that etches both of the BARC (bottom anti-reflective coating) material and the gate electrode material having the one of an N-type dopant or a P-type dopant. An etch rate of the gate electrode material having the one of an N-type dopant or a P-type dopant in the etching reactant increases with an increase of the dopant concentration of the one of an N-type dopant or a P-type dopant in the gate electrode material. Sidewalls of the gate structure are trimmed by a trim length during the step of stripping the BARC (bottom anti-reflective coating) material from the gate structure. Thus, the dopant concentration of the one of an N-type dopant or a P-type dopant in the gate electrode material is adjusted to control the trim length of the gate structure.
In another aspect of the present invention, an additional neutral dopant is implanted into the layer of gate electrode material such that the neutral dopant has a neutral dopant concentration in the layer of gate electrode material before the step of depositing the layer of BARC (bottom anti-reflective coating) material. The etch rate of the gate electrode material having the neutral dopant in the etching reactant increases with an increase of the neutral dopant concentration in the gate electrode material. Thus, the neutral dopant concentration of the neutral dopant in the gate electrode material is also adjusted to further control the trim length of the gate structure.
The present invention may be used to particular advantage when the gate electrode material is comprised of polysilicon, the neutral dopant is comprised of germanium, the BARC (bottom anti-reflective coating) material is comprised of silicon oxynitride (SiON) having a thickness in a range of from about 150 xc3x85 (angstroms) to about 250 xc3x85 (angstroms), and the etching reactant is comprised of phosphoric acid (H3PO4).
In this manner, the side walls of the gate structure are trimmed down to reduce the length of the gate structure beyond that achievable with photolithography processes with control of the trim length by adjusting the doping of the gate structure. In addition, the side walls of the gate structure are trimmed down during the step of stripping the BARC (bottom anti-reflective coating) material from the gate structure such that additional processing steps are minimized.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.